Due to the requirements of the various consumer electronics products are dramatically increasing, different kinds of electrical devices having multi-functions and high responding speed are getting more and more popular. One of the core circuits of such a high-speed and delicate electrical system is the DLL. The main function of a DLL is to synchronize the internal signals of an electrical system and the external signals such that the electrical system could be operated stably and normally. The DLL has various configurations. Classified according to the nature of signals, there are two kinds of DLLs: the digital DLLs and the analog DLLs.
The conventional digital DLLs include the register controlled DLL and the counter controlled DLL. However, the digital DLLs have their unavoidable constraints of using the extra digital controlling circuits to control the DLLs. But for such a digital DLL, relatively the chip size is larger, the power consumption is higher and the accuracy of the delay function is lower.
On the contrary, each of the analog DLLs employs an internal VCDL to achieve the purpose of controlling its delay. A loop voltage is employed to control the cascaded delay cells so as to achieve the desired delay value. Compared with the digital DLLs, the main advantage of the analog DLLs is that the relatively higher accuracy of the generated delay such that relatively the analog DLLs are more frequently employed in the applications of systems requiring higher frequency and higher accuracy regarding their delays.
VCDL is one of the various core circuits of the analog DLLs. Classified according to the configurations, there are two kinds of VCDLs: the active VCDLs and the passive VCDLs. The passive VCDLs employ the passive delay cells including the passive elements such as the resistors and the capacitors. On the other hand, the active VCDLs employ the active delay cells which include MOSFETs. The advantage of the passive VCDLs is that the power consumptions of which are relatively lower, and the disadvantage of which is that the chip sizes of which are relatively larger when the systems requires relatively higher delays. And, the features of the resistors and capacitors are easily influenced by the manufacturing process so as to influence the accuracies of the delay cells. The advantage of the active VCDLs is that the accuracies of which are relatively higher, and the disadvantage of which is that the power consumptions of which are relatively larger. However, both of the active and the passive DLLs are facing the same problem that is if the system requires relatively more detailed delays, relatively the analog DLL would require more delay cells, and again the analog DLLs are facing the same dilemma of larger chip sizes and larger power consumptions. Besides, relatively the noise signals are more significant so as to influence the functions of the DLL when there are more electronic elements.
To improve the above-mentioned problems, one of the thorough solutions is to decrease the number of the delay cells. Although mentioned in the prior art regarding to decrease the number of the delay cells via one of the array arrangement method and the interpolator method, extra digital control circuits are required such that errors are easily generated and the accuracies of the delays are decreased.
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the applicants finally conceived the delay lock loop and the phase angle generator.